With much excitement and anticipation, we are happy to announce the return of this competiton. This event is an FPGA Programming Competition made possible thanks to the sponsorship of Altera and Impulse Accelerated Technologies and the leadership of the Ottawa section of the IEEE. With much effort, we held our first event in the Winter of 2008; and having learnt from that experience, we would like to invite North-American students to participate in an improved format. We have decided to make two changes to benefit more students and also to provide a more complete scope of the design cycle: First, we are now welcoming student teams from North-American institutions; second,  the event will span both Fall and Winter semesters.

Innovate North-America is open to undergraduate and masters students enrolled in a Canadian or American college or university. Knowledge of Verilog/VHDL/C is desirable and recommended but not required to participate, but knowledge of digital design or computer/system architecture is key.
The spirit of this competition is to provide a venue for students to gain practical experience in implementing an innovative under some of the constrains and conditions they will face in industry. An abstract of the winner's work will be published in one of the IEEE publication; for example, an article about the 2009 winner's appeared in the summer publication of the IEEE Canadian Review.

Innovate North-America brings together Canadian and American students and mentors from academia to a learning environment encouraging innovation. Each team must have a mentor from the institution they are enrolled in, and in some cases they may chose a mentor from industry. Each team should also have at least one member knowledgeable in digital design or computer/system architecture. FPGA design experience is desirable but not required.

Design projects will be judged on their innovation, quality of final report, completeness, practicality and complexity; the most important factor being innovation and quality of final report. Teams with masters students will have their score handicaped to make it fair for undergrad student. Points will be awarded to teams showing their designs running on the evaluation board provided.

If you are interested to share your industry or teaching experience as a mentor, this is the event for you! Please register using the link on the left, fill up the form making sure to add relevant information that would help our team-mentor matching process. Do not hesitate to contact us if you have any questions, or if you want to give us feedback!

You can join our forum now by hitting the register link on the left and filling the form. See Frequently Asked Questions for more details.
Innovate North-America FPGA design competition Nov/2009-Mar/2010
Check out the Frequently Asked Questions for details (like deadlines, for example).
Automatic Object Recognition Algorithm by University of Toronto Team Wins Altera/IEEE/Impulse Innovate Canada Competition
University teams develop innovative solutions for image processing, medical electronics and embedded control
Altera Corporation (NASDAQ: ALTR), IEEE Canada and Impulse Accelerated Technologies would like to announce the winners of the Innovate North-America Programming competition. This competition provided student teams with leading edge Altera FPGA based development boards, FPGA design tools from Altera and C-to-FPGA tools from Impulse, and engineering support from both companies in their efforts to develop commercially useful and innovative applications.

All of the resulting applications will be made available to the public via this website
First prize went to a team mentored by Dr. Gregory Steffan at the University of Toronto. Team members Martin Labrecque, Muttee Sheikh, Jill San Luis, Benzakhar Manashirov and Mohammed Elsayed created an FPGA-based object recognition project that included a number of complex hardware filters as well as software running on an embedded NIOS 2 processor. Second prize went to an Ottawa University team Mentored by Dr. Miodrag Bolic. Team members Daniel Shapiro, Vishal Thareja, Saurabh Ratti, Srivatsan Vijayakumar and Muran Yang created an automatic fuzzy logic generator, including compiler extensions, that enhances the instruction set of the open-source LEON embedded processor. Third place was a tie; a Carleton University team, composed of Trevor Burton and Geoffrey Green and again Mentored by Dr. Miodrag Bolic, created a hardware implementation of a wavelet‐based image compression algorithm. Also tied for third place was the University of Saskatchewan team mentored by Dr. Eric Salt. Team members Geoff Baker, Shea Pederson, Adrien Rudulier, Nathan Windels and Brett Baerg created a hardware system for Ethernet transmission of MPEG stream from standard composite (yellow RCA) NTSC. Honorable mention also went to the Carleton University team mentored by Dr. Adrian Chan and Dr. Sreeraman Rajan. This team, composed of students Daanish Khan and Dragan Trifkovic, created a heart rate estimator using phonocardiogram (PCG) signals to automate unattended unobtrusive heart rate estimation.