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Sample behavioral waveforms for design file ram2.v

The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design ram2.v. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design ram2.v has two read/write ports. Read/write port A has 1024 words of 8 bits each and Read/write port B has 1024 words of 8 bits each. The A core uses a different clock enable than the A input registers. The B core uses a different clock enable than the B input registers. The output of the read/write port A is unregistered. The output of the read/write port B is registered by UNREGISTERED.

Fig. 1 : Wave showing read operation.

The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled.

Fig. 2 : Waveform showing write operation

The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the falling edge of the write clock. The clock enable on the write side input registers are disabled. During a write cycle on a port (A or B), the new data flows through to the output of the same port.